The invention relates to a circuit arrangement for the bidirectional transmission of binary signals. The circuit arrangement is connected between a line, and a bus. The line is connected to one pole of a voltage source via at least a first resistor. The bus is connected to at least one data transmitter which is low-ohmic for only one binary signal value. The bus is also connected to at least one data receiver which has a comparatively high input resistance.
A circuit arrangement of this kind is used for connecting a sub-system, via said line to a corresponding subsystem. The former subsystem is formed from a plurality of individual arrangements which are situated near one another in space and which are connected by a short bus. The latter subsystem, however, is situated in a remote location with respect to the former subsystem and may also comprise a bus when the latter sub-system includes more than just one data transmitter and one data receiver. Each bus is also connected, via a resistor, to the one pole of the voltage source. A data transmitter customarily consists of a transistor which is connected between the bus and the other pole of the voltage source. The transistor connects the bus to the other pole of the voltage source, customarily the 0 volt potential of the overall system, for the one binary value of the data to be transmitted. Subsequently, the transistor in the data transmitter is turned off and the potential on the bus line again assumes the voltage value of the one pole of the voltage source, which is customarily +5 volts.
In high-frequency data transmission, the capacitance of the bus with respect to the environment gives rise to a problem. That is, for a signal transition to 0 volts the capacitance of the bus can be comparatively quickly discharged by the turned-on transistor in the data transmitter. However, when the transistor is turned off, the signal on the bus increases according to the time constant of the capacitance represented by the bus and the resistor connected to the +5 volts. The value of this resistor is limited by the current loadability of the transistors in the data transmitters, because they are generally included in integrated circuits so that only a limited crystal surface area is available and the loss of power may not become excessively high. Therefore, for a predetermined transmission speed or data rate the length of the bus is limited. An improvement can be achieved by replacing the resistor, which connects the bus to the one pole of the voltage source, by a current generator. However, this solution offers only minor improvement and is relatively expensive.
Therefore, for high-speed transmission of binary data via a bidirectional connection, the described circuit issued. The circuit is marketed, for example, as an integrated circuit of the type SN 74 LS 243. For a bus, such an integrated circuit comprises: an output amplifier which applies the signal present on the bus to a longer connection line in a low-ohmic manner; as well as an input amplifier which applies the signal from the connection line to the bus. For reasons of stability and current consumption, only one of the amplifiers is activated by means of control signals. The relevant control signals must ensure that it is impossible for the two amplifiers to be activated simultaneously. For easier operation of such transmitter/receiver circuits, for example integrated circuits of the type SN 74 LS 245, comprise internal combinatory logic elements to ensure that only one signal direction is enabled. In any case, however, the relevant control signals must be present for reversing the signal direction. A circuit arrangement in which the transmission direction is automatically reversed without control signals or by means of given constant control signals is known. An example is an integrated circuit of the type 8X41. This known circuit, however, is very complex and enables reversal of the transmission direction only when both the bus and the connection line carry a high potential.